The present invention relates to pulse width modulation in power converters, and more specifically to Fixed Frequency Ripple Regulator modulation.
A simplified diagram of a synthetic ripple regulator pulse width modulation (PWM) converter is shown in FIG. 5. In this type of converter, an error amplifier EA provides an error signal to a synthetic ripple regulator (SRR) that provides PWM pulses to drive the output stage comprising transistors Q1 and Q2. These regulators provide a fast response to a load transient. The switching frequency of the converter 5 is not fixed and the converter operates asynchronously.
FIG. 1 shows the SRR. The output of the error amplifier 10 is fed to inputs of hysteresis comparators 40 and 42 to provide reset and set signals to a flip-flop circuit 14. The switching stage 16 includes high and low power transistors Q1 and Q2 connected at a switching node 18, which is coupled to a capacitor 22 through an inductor 20. The power transistors may be MOSFETs and are switched complementarily.
FIG. 1 illustrates the SSR having transconductance amplifiers 30 and 32, which respectively convert the voltages VIN and VO into currents that charge and discharge a ripple capacitor 34. A transistor Q3, controlled by the PWM signal provided by the flip-flop circuit 14, is coupled between output terminals of the amplifiers 30 and 32.
The positive slope of voltage VR at node 36 can be written as:VRPOS=gm·(Vin−Vout)and the negative slope of VR can be written as:VRNEG=gm·Vout,where gm is the gain of the transconductance amplifiers.
The Synthetic Ripple Regulator of FIG. 1 has comparators 40 and 42. The comparator 40 controls a negative going edge of the PWM signal by providing a resetting signal to the flip-flop circuit 14 when the voltage VR across the capacitor 34 exceeds the sum of the predefined window voltage value Vwindow (VW) and the error amplifier output signal EA. The comparator 42 controls a positive going edge of the PWM signal by providing a setting signal to the flip-flop circuit 14 when the voltage VR across the capacitor 34 falls below the level of the error amplifier output signal EA.
FIGS. 3a and 3b illustrate operation of the SSR for a load step up and load step down. The ripple voltage across CR is determined between EA and EA+Vwindow, the window voltage. When the ripple voltage VR drops below EA, the flip-flop 15 is set so the PWM pulse starts. When the ripple voltage exceeds EA+VW, the flip-flop is reset and the PWM pulse terminates. The duty cycle of the PWM pulse is determined by comparing the EA output to the ripple voltage. FIG. 3a shows a load step-up (increased load current) response and FIG. 3b shows a load step-down (decreased load current) response. As illustrated, during the transient, the SRR modulator (see FIG. 1) changes switching frequency to effectively have the desired dynamic duty cycle to compensate output voltage change. Thus, as the output voltage Vout decreases in FIG. 3a in response to a load step-up, the duty cycle increases and as the output voltage increases in response to a load step-down, the duty cycle decreases.
While Synthetic Ripple Regulator (SRR) modulation technology claims the fastest response, SRR modulation has inherent shortcomings. Such shortcomings include variable frequency operation and difficulty of implementation in multi-phase applications.